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NIOS FAQ

Version 3, changed by chrismonkey. 12/20/2006.   Show version history

NIOS FAQ

Q1) When I try to open a Quartus project, I get the error "Error: Can't open project -- you do not have permission to write to all the files or create new files in the project's database directory."  What do I do?

Create a file called fix.bat in your project directory and add these commands to it:
attrib -R /S /D *
attrib -R /S /D .
Double click the batch file to run it & you should be all set.

Q2) When I run the FLASH programmer or try to download code in the IDE I get an error like this:
Reading System ID at address 0x009018F8: does not match
    ID value does not match: read 0x81C61B05; expected 0x5F86888B
    Timestamp value does not match: image on board is older than expected
    Read timestamp 12:03:33 2006/11/17; expected 16:07:38 2006/11/30

Your FPGA has to be loaded up with the same NIOS CPU that you've compiled your program for.  The programmer checks this before downloading the code and bails out if they don't match. 

If your NIOS system doesn't include a System ID component, you can disable the check.  On the Run Window's Main tab, uncheck "Validate NIOS II System before software download"

If you do have a System ID component, then either you modified your NIOS system in SOPC builder since you generated it, or you didn't load the correct FPGA image.  The expected values are taken from the project's .ptf file.  If the .ptf file is newer than the .sof file, you'll have this problem.  Regenerate the NIOS system, rebuild the FPGA, and recompile the program.
Q3) How do I fix intermittent failures on the JTAG interface?
Make sure you have 10K pull-up resistors on TMS & TDI and a 10K pull-down resistor on TCK. 
Add bypass capacitors to the 3.3V and GND connections on the JTAG header.

If you're using a USB Blaster Rev B, contact your FAE to trade it in for a Rev C.  The Rev B units are known to be susceptible to noise problems.


Comments (1)

jasoncole said, 11/07/2007:

Re: (Q3). Adding schmitt buffers can help, as well as keeping all tracks short, thus minimising the potential for clock double-triggering.

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